NXP Semiconductors /LPC43xx /GIMA /ADCHS_TRIGGER_IN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ADCHS_TRIGGER_IN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NOT_INVERTED)INV 0 (NO_EDGE_DETECTION)EDGE 0 (DISABLE__SYNCHRONIZ)SYNCH 0 (DISABLE_SINGLE_PULSE)PULSE 0 (GPIO6_28)SELECT0RESERVED

EDGE=NO_EDGE_DETECTION, SYNCH=DISABLE__SYNCHRONIZ, PULSE=DISABLE_SINGLE_PULSE, SELECT=GPIO6_28, INV=NOT_INVERTED

Description

ADCHS trigger input multiplexer (GIMA output 24)

Fields

INV

Invert input

0 (NOT_INVERTED): Not inverted.

1 (INPUT_INVERTED): Input inverted.

EDGE

Enable rising edge detection

0 (NO_EDGE_DETECTION): No edge detection.

1 (RISING_EDGE_DETECTIO): Rising edge detection enabled.

SYNCH

Enable synchronization

0 (DISABLE__SYNCHRONIZ): Disable synchronization.

1 (ENABLE__SYNCHRONIZA): Enable synchronization.

PULSE

Enable single pulse generation.

0 (DISABLE_SINGLE_PULSE): Disable single pulse generation.

1 (ENABLE_SINGLE_PULSE): Enable single pulse generation.

SELECT

Select input. Values 0xA to 0xF are reserved.

0 (GPIO6_28): GPIO6[28]

1 (GPIO5_3): GPIO5[3]

2 (SGPIO10): SGPIO10

3 (SGPIO12): SGPIO12

4 (RESERVED): Reserved

5 (MCOB2): MCOB2

6 (CTOUT_0_OR_T0_MAT0): CTOUT_0 or T0_MAT0

7 (CTOUT_8_OR_T2_MAT0): CTOUT_8 or T2_MAT0

8 (T0_MAT0): T0_MAT0

9 (T2_MAT0): T2_MAT0

RESERVED

Reserved

Links

()